library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity vm is
	generic
	(
		DATA_WIDTH	: natural  :=	32;
		MODE_WIDTH	: natural  :=	2
	);

	port
	(
		-- Input ports
		--mode	: in  std_logic_vector(MODE_WIDTH-1 downto 0);
		vaddr	: in  std_logic_vector(DATA_WIDTH-1 downto 0);
		
		-- Output ports
		maddr	: out std_logic_vector(DATA_WIDTH-1 downto 0)
	);
end vm;

architecture rtl_vm of vm is
constant m1offset : std_logic_vector(DATA_WIDTH-1 downto 0) := X"C0000000";
begin
	process (vaddr)
	begin
		case vaddr(31 downto 6) is
			when B"00000000000000000000000000" => maddr <= B"00000000000000000000000000" & vaddr(5 downto 0);
			when B"00000000000000000000000001" => maddr <= B"00000000000000000000000001" & vaddr(5 downto 0);
			when B"10000000000000000000000000" => maddr <= B"00000000000000000000000010" & vaddr(5 downto 0);
			when B"10000000000000000000000001" => maddr <= B"00000000000000000000000011" & vaddr(5 downto 0);			
			when others => NULL;
		end case;
	end process;
end rtl_vm;

